1. Field of the Invention
The present invention relates to an information processing apparatus including a WideIO memory device stacked on an SOC die having a CPU, a control method for the information processing apparatus, and a computer-readable storage medium.
2. Description of the Related Art
In an existing information processing apparatus, a DRAM (Dynamic Random Access Memory) is generally used to save data for executing an OS and various applications, and to temporarily save data for executing image processing. This DRAM is used as it is connected to a CPU, an SOC, or the like. Recently, the memory bandwidth of the DRAM is increasing as information processing apparatuses become multifunctional and improve in functionality. To increase the memory bandwidth, the clock frequency of data access is raised in standards such as DDR3 or DDR4. In addition, the bandwidth is allocated by using a plurality of DRAM channels connected to a CPU or ASIC.
However, raising the clock frequency or using a plurality of memory channels poses the new problem that the power consumption increases. WideIO as the next-generation DRAM standard is presently attracting attention. WideIO is a memory technique of stacking a DRAM chip on an SOC die by adopting a 3D stacking technique using a TSV (Through Silicon Via). WideIO has the features that a high bandwidth of a maximum of 12.8 GB/sec or more is obtained with a large data width of 512 bits, and the power consumption is low because the access frequency is lowered. Furthermore, the use of the TSV can make the package thinner and smaller than that of a conventional PoP (Package on Package) structure. More specifically, as a measure against heat in a structure stacking a memory in an SOC package, a temperature sensor is integrated to change the self-refresh rate according to the temperature. Furthermore, WideIO has the feature that the 512-bit data width is divided into four 128-bit channels and these channels are controlled independently of each other. For example, it is possible to set channels 1 and 2 in a self-refresh state, and use channels 3 and 4 in a normal state. The basic structure of WideIO and a technique associated with a basic access method are proposed in U.S. Patent Application Publication No. 2012/0018885.
The aforementioned conventional technique has the following problems. That is, the multilayered structure of WideIO is susceptible to the influence of heat. For example, when a specific region of the die and the WideIO DRAM positioned above this specific region are simultaneously activated, the temperature of the activated portions locally rises. This increases a semiconductor leakage current that exponentially increases with respect to the temperature, resulting in large power consumption. The DRAM stores data by accumulating charges in the capacitor of each cell. Since, however, the capacitors are spontaneously discharged by the semiconductor leakage current, the DRAM needs to charge the capacitors by a refresh operation. Discharging depends on the temperature. That is, as the temperature is higher, the discharge speed is also higher. If, therefore, the temperature becomes higher, it is necessary to increase the refresh frequency. Consequently, the power consumption by a refresh operation increases or the access performance of the DRAM decreases because the DRAM cannot be accessed during a refresh operation.
Especially, a memory layer closest to the SOC die directly contacts the SOC die, and its temperature thus becomes very high. If, therefore, the memory layer closest to the SOC die is accessed, the adverse influence such as an increase in power consumption or a decrease in access performance becomes larger. To reduce the adverse influence due to a high temperature, it is necessary to control to preferentially access a memory layer at a low temperature.